B.TECH - Semester 3 digital system design Question Paper 2020 (may)
Practice authentic previous year university questions for better exam preparation.
Sample Questions
- Write the canonical POS expression for the given function, $f(x, y, z)=\pi M(0,2,3,6)$.
- Realize a XOR gate with NAND only circuit and give the truth table also.
- Give the schematic diagram for the 2-bit binary adder and explain the working of the same.
- Realize a D Flip Flop and T-Flip Flop with a JK Flip Flop.
- What is a Universal Shift Register?
- Differentiate between static RAM and dynamic RAM.
- Why the state diagram is necessary for simplification of a sequential circuit'?
- List the limitations of asynchronous counter,
- How the divide-overflow problem can be avoided?
- What is partial product multiplier? (Answer one question from each Module. Each question carries 20 marks.)
- (a) Using a four variable K map, simplify the given expression, $$ f=\sum m(1,3,4,6,9,11,13,14) $$
- (b) Design a full subtractor and implement the with the help of logic gates.
- (a) Reduce $f=\sum(0,1,2,3,6,7,8,12,13,15)$ using Quine Mccluskey method.
- (b) A four bit binary number is represented by $A_{3} A_{2} A_{1} A_{0}$ where $A_{1}$ is LSB. Design a combinational logic circuit so that output is high when binary number is greater than 0010 but less than 1000.
- (a) Realize the given Boolean expression with a $16: 1$ multiplexer, $Y(D, C, B, A)=\sum m(0,2,6,8,9,11,13,15)$.
- (b) What is race condition in JK FF? How it can be solved with JK Master Slave FF circuit? Explain with the help of necessary diagrams.
- (a) Realize the given Boolean expression with a $16: 1$ multiplexer, $$ Y(D, C, B, A)=\prod M(1,4,6,9,10,11,14,15) $$
- (b) Briefly discuss about different types of shift registers.
- (a) Write a VHDL code for realizing 4:1 multiplexer.
- (b) The capacity of $2 \mathrm{~K} \times 8 \mathrm{PROM}$ is to be expanded to $16 \mathrm{~K} \times 8$. Find the number of chips required and the number of address lines in the expanded memory.
- (c) Draw the neat diagram of a PLA and explain the functions of each component.
- (a) A combinational circuit is defined by the function
- (i) $\quad F_{1}(A, B, C)=\sum(3,5,6,7)$ (ii) $\quad F_{2}(A, B, C)=\sum(0,2,4,7)$ Implement the circuit with a PLA having three input four products term and two outputs term.
- (b) Draw the logic circuit of a mod-JO BCD synchronous counter and explain the operation with the help of a timing diagram.
- (a) Design a multiplier for multiplying two 8 -bit numbers by using twoscomplement fractions algorithm. 10
- (b) Briefly discuss about high speed adders. OR
- (a) Describe the steps involved in restoring and non-restoring division?
- (b) How the multiplication performance has improved by using Booth's multiplication algorithm ? Explain.