B.TECH - Semester 8 computer system architecture Question Paper 2008 (may)
Practice authentic previous year university questions for better exam preparation.
Sample Questions
- A benchmark Program with 50000 Integer, 40000 Data Transfer, 10000 Floating Point and 8000 Control Instructions is executed on a 100 MHz processor. The instructions require $1,2,2$, and 2 clock cycles respectively for execution. Calculate the CPI, MI...
- Explain the Omega and Crossbar interconnect network.
- Explain the detection of parallelism with Bernstein's conditions. Is this an efficient technique? Justify.
- Consider a two-level memory hierarchy $M_{1}$ and $M_{2}$ with access times $t_{1}$ and $t_{2}$, cost per byte $c_{1}$ and $c_{2}$, and capacities $s_{1}$ and $s_{2}$ respectively. The first level memory hit ratio $\mathrm{h}=0.9$. Calculate the effe...
- What are the design trade-offs between large register files and large D-Cache?
- Compare the pipelining in vector processors and scalar processors. What are the limiting factors of degree of superscalar design?
- A non-pipelined processor $P_{1}$ has clock rate of 100 MHz and an average CPI of 4. $P_{1}$ is improved to $P_{2}$ as a pipelined processor with 5 -stage linear instruction pipeline and reduced clock rate of 80 MHz (due to latch delay). What is the ...
- Explain the Write-Once cache coherence protocol.
- Explain S-access, C-access and C/S-access memory organizations for vetor accesses.
- What are the context switching policies in multi threaded architectures? ( $10 \times 4=40$ Marks) Answer any ONE full question from each module.
- Describe Parallel Random-Access Model and the variants. Explain any one of the variant in the context of an $n \times n$ matrix multiplicaiton. Discuss the time complexity. (20)
- (a) Write a note on the Data-Routing Function in interconnect.
- (b) Compare the Multi-Processor, Message-Passing, Multi Vector and SIMD architectural models.
- (a) Explain the collision free scheduling with an example.
- (b) With a neat diagram explain the address translation with TLB.
- Explain the superscalar pipeline design in detail. Explain the in-order and out-of-order issue of instructions with an example. (20)
- (a) Explain the performance-directed design goals of super computers. Use examples wherever possible.
- (b) With a note on the six common types of vector instructions.
- Explain the prefetching and relaxed memory put space consistency models for hiding latency in MPPs. $$ (3 \times 20=60 \text { Marks }) $$