B.TECH - Semester 6 vlsi design Question Paper 2019 (jun)
Practice authentic previous year university questions for better exam preparation.
Sample Questions
- 602 : VLSI DESIGN (TA) Time : 3 Hours Max. Marks : 100 Answer all questions : Each question carries 4 marks :
- Enumerate the steps of IC fabrication.
- What is meant by MBE ? Explain.
- State and explain Ficks law.
- What is the effect of channel length modulation in performance of a device? Explain.
- Draw the layout and the stick diagram of a CMOS inverter.
- Draw the circuit of a pseudo NMOS. What is the specialty of this circuit?
- Draw the diagram of a Carry Bypass Adder and explain the working.
- Explain the testing methods of VLSI circuits.
- Differentiate between PAL and PLA.
- Explain the advantages of FPGA based design. Answer any two questions from each module. Each question carries 10 marks.
- With neat sketches explain CZ process for crystal growth.
- Explain various methods for lithography. Draw necessary diagrams.
- Explain (a) n-well process (b) p-well process (c) twin tub process.
- With necessary diagrams explain VLSI design flow in detail.
- (a) Draw and explain the DC characteristics of a CMOS inverter with necessary conditions for various regions of operation.
- (b) Find the sub threshold leakage current of an inverter at room temperature if the input $A=0$. Let $\beta n=2 \beta p=1 m A V^{2}, n=1.0$, and $\left|V_{t}\right|=0.4 \mathrm{~V}$. Assume the body effect and DIBL coefficients are $\gamma=\eta=0$.
- (a) State and explain the $\mu$ and $\lambda$ design rules.
- (b) What is meant by pass transistor logic? Design a XOR gate using pass transistor logic.
- Explain the concept of Carry Look Ahead adder with neat diagrams.
- Explain the principle of operation of (a) Register based multiplier and (b) Array multiplier.
- Write short notes on (a) Test generation methods (b) Dynamic memory latches. ( $6 \times 10=60$ Marks) G - 3274