B.TECH - Semester 6 vlsi design Question Paper 2020 (sep)
Practice authentic previous year university questions for better exam preparation.
Sample Questions
- 602 : VLSI DESIGN (TA) (2008 Scheme) Time : 3 Hours Max. Marks : 100 Answer all questions. Each question carries 4 marks.
- Explain Deal Grove model.
- Give the principle of Ion Implantation process.
- What is the need for isolation in VLSI chips? Give any two methods for the same.
- Explain the operation of NMOS in saturation region.
- Define noise margin in VLSI circuits. Give the factors affecting noise margin.
- Draw a half adder circuit using TG logic.
- Draw the circuit diagram of a Carry Look Ahead adder.
- Explain the principle and types of sense amplifier.
- With an example, explain the features of a VLSI design rule.
- Enumerate the steps in FPGA based VLSI design. Answer any two questions from each module. Each question carries $\mathbf{1 0}$ Marks.
- Explain various methods for oxidation with neat sketches.
- What is the significance of deposition process in IC fabrication? Discuss various methods for the same.
- What is meant by SOI ? Explain the fabrication steps of SOI.
- What is the need for scaling in VLSI circuits? Discuss various techniques employed for scaling.
- (a) Explain short channel and secondary effects in MOSFETS.
- (b) A 90 nm long transistor has a gate oxide thickness of $16 \AA$. What is its gate capacitance per micron of width?
- Differentiate between static and dynamic power dissipation. Explain the same in a CMOS inverter.
- Explain with neat sketches (a) Linear Carry Select Adder
- Explain with neat sketches (b) Square root Carry Select Adder.
- Draw and explain the conventional, pulsed and resettable latches.
- What is meant by the design for testability? Explain in detail. ( $\mathbf{6} \boldsymbol{\times} \mathbf{1 0} \boldsymbol{=} \mathbf{6 0}$ Marks)