B.TECH - Semester 8 computer system architecture Question Paper 2019 (nov)
Practice authentic previous year university questions for better exam preparation.
- What is the need for cache coherence mechanisms?
- Briefly describe cache coherence problems.
- Differentiate implicit and explicit parallelism.
- (b) Define (i) speedup (ii) efficiency (iii) throughput of a processor pipline.
- (a) Consider the following reservation table for four stage pipeline with clock cycle $=20 \mathrm{~ns}$.
- Discuss briefly about Flynn's classification of computer architecture.
- Compare the features of NUMA and COMA models.
- (b) Explain the differences between UMA, NUMA, COMA model with neat diagram.
- Define CPU time and CPI List the factors contributing to measure CPU time.
- What are the features of parallel random access machines?
- What is TPS and KLIPS rating?
- What is scoreboarding? How this technique improves pipeline performance?
- What are hot spots? How they degrade system performance? ( $\mathbf{1 0} \boldsymbol{\times} \mathbf{4} \boldsymbol{=} \mathbf{4 0}$ Marks) P.T.O. Answer any one full questions from each Module．Each question carry 20 marks 11．（a）Explain the generic model of a message passing multiprocessor． 8 （b）D...
- (a) What are the advantages of using vector processors? Discuss briefly about the vector processing principles.
- (b) Discuss briefly about multi-vector multi processing.
- (a) Explain the implementation models of SIMD computers. 10
- (b) Discuss briefly about scalability issues of SVM architectures. 10 ( $\mathbf{3} \boldsymbol{\times} \mathbf{2 0} \boldsymbol{=} \mathbf{6 0}$ Marks)
- What is the significance of Bernsteins's condition in determining parallelism in programs?
- Differentiate between synchronous and asynchronous model of linear pipline processors.
- Distinguish between static and dynamic dataflow computers. Answer all questions.
- (a) Explain the various parameters used for evaluation of system performance. Write its significance.
- (a) What are the different types of data, control and structural hazards pipelined processors. How these hazards can be resolved?
- (b) Describe briefly about operational model of SIMD computers with an example.
- (a) Explain the importance of memory hierarchy. How the performance of a memory hierarchy is determined?
- (b) What are the different types of interleaved memory organization and it advantage?
- (a) Explain the different types of vector architecture.
- (b) Write a note on VLIW processors and its pipeline operation.
- (i) What are the forbidden latencies and the initial collision vector? (ii) Draw the state transition diagram. (iii) Determine the MAL associated with the greedy cycle. (iv) Determine the pipeline throughput corresponding to the MAL.
- (v) Determine the lower bound on the MAL for this pipeline. | x | | | | | x | | :--- | :--- | :--- | :--- | :--- | :--- | | | x | | x | | | | | | x | | | | | | | | x | x | |
- (a) Explain the mechanism for instruction pipelining. ..... 10
- (b) Explain Tomasulo's algorithm for dynamic instruction scheduling. ..... 10 Module - IV
- (a) Explain blocking and non blocking network with the help of a 8 input Omeganetwork. Explain routing from P4 to P7.15
- (b) Write notes on cross bar network used in multiprocessor interconnectionnetwork.5 ## 13. Explain the following
- (a) Full map directory based protocol. ..... 10
- (b) Snoopy bus protocol. ..... 10
- What is a backplane bus? What is its use?
- What is random parallelism? How is it exploited in VLWI computers?
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