B.TECH - Semester 5 computer organisation and architecture Question Paper 2021 (dec)
Practice authentic previous year university questions for better exam preparation.
- 503 COMPUTER ORGANISATION AND ARCHITECTURE (TA) (2008 Scheme) Time : 3 Hcurs Max, Marks : 100 PART - A Answer all questions.
- Explain R-wpe instruction formal with an example.
- Define CPI. Compare the performance of the given two processors. | | Clock Rate | | CPI | | :---: | :---: | :---: | :---: | | P 1 | 2 | | 2 | | P 2 | 3 | | 2,5 |
- What are the different instruction types used in MIPS assembly?
- Differentlate single precision and double precision representation of floaling point numbers. 5 Draw the data palh for 'jump' instruction in MIPS.
- What are the disadvanlages of Single cycle implementation scheme?
- What are Branch hazards? Explain with an example. 8 Distinguish belween 'wrile back' and 'write ihrough' prolocoi in cache memory. P.T.O.
- What is the role of TLB in address lianslation?
- Give the functions of the following 8086 Pins (a) READY
- Give the functions of the following 8086 Pins (b) ALE
- Give the functions of the following 8086 Pins (c) HOLD Answer any two questions from each Module. Each question carries 10 Marks.
- (a) Convert the following C program inla MIPS language loop: $\mathrm{g}=\mathrm{g}+\mathrm{A}[\mathrm{i}] ;$ $\mathrm{i}=\mathrm{i}+\mathrm{j}$, If ( $i!=$ h) go to loop:
- (b) Represent the number -13.456 , in double precision floating paint notation.
- (a) Explain different addressing modes of MIPS with examptes. 5
- (b) Compare RISC and CISC architectures.
- Explain the algorithm for binary division with an example.
- With the help of necessary control signals, draw and explain the Single cycle implemenlation scheme. 15 Explain Hardwired and Microprogrammed control unil with neat sketches.
- Explain Pipelined dala palh and control.
- Draw and explain the internal archilecture of 8086 microprocessor.
- (a) Discuss the concept of Virtual memory.
- (b) Wrile a nole on DMA data transfer mechanism.
- Explain different Mapping lechniques in cache memory.
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